In our design, we decided to completely remove the existing cotnrol system becasuse it was all on one board. We are replacing it with use a Cyclone V as our processing unit. It has an ARM processor on the same chip as an FPGA. The ARM processor can run linux which allows for easier troubleshooting and allows the use of scripting languages such as Python. The advantage of the FPGA is that is allows for customization of the I/O for future applications. For example the ESP has a camera which is used to determine the locations for sampling. The FPGA could do initial processing of the data from the camera. Also the FPGA would allow the control system to be adapted to control other applications with now redesigning of the system’s hardware. The FGPA will be connected to commertial motor drivers.
The limit switches will be mounted to the system as shown below. These limit switches will allow the system to home and act as hardware safety interlocks. If a limit switch is pressed then the motor will not be allowed to move in the direction of the limit switch. To home the system the arms will be moved until X1 and Y1 are pressed, and the FPGA will set the memory locations that hold the current position for the x and y axes to zero. The z direction will use the existing optical switch in the column to determine the zero position. After the system is homed, it will record the outputs from the x and y encoders and add or subtract accordingly from the current position.
Each
motor
will have its own driver which is the G213V Digital
Step Drive. This
driver can connect 4, 6, or 8 lead wires into any desired
configuration.
With a max current of 7 amps it can be used to drive each
individual
motor. The driver has twelve total pins; four pins for the motor
connection,
two for input power and grounding, four pins for communication with
FPGA, and
the final two for setting current.
Erin - 1/08 - 1/20: Write a program to get the hard processor to communicate to the computer over ethernet.
1/20 - 2/3: Write a script to interpret commands sent over ethernet, start on C programs to read and change memory
2/3 - 3/20: Finish C programs, troubleshoot errors in communication and on the hard processor
3/20 - 3/28: Develop the user interface
3/31 - 4/18: Testing user interface with outside people
Brian - 1/8 - 1/20: Map all of the memory address and configure the bridge between the hard processor and FPGA using Qsys
1/20 - 2/5: Program a square wave to be connected to the step input of the motor driver and a direction line in Quartus
2/5 - 2/10: Verify output is correct for the motor drivers
2/10 - 3/17: Program motor controller for the FPGA in Quartus and help program the C interface for the hard processor
3/17 - 3/31: Test the motor controller
3/31 - 4/18: Debug problems found during testing
Seth - 1/8 - 1/20: Test driver, and order drivers for each axis
1/20 - 2/10: Build and test wiring harness
2/10 - 2/17: Test the wiring harness with the Cyclone V
2/17 - 3/3: Build mounting hardware for the electronics
3/3 - 3/17: Mount the limit switches
3/17 - 4/18: Debug problems found during testing
All
- 4/18
- 4/24:
Finish documentation and prepare for the design fair